Imaging Systems Laboratory: Research on Computation LithographyObjectiveWe develop computational algorithms — mostly inverse imaging — for optical lithography in IC manufacturing. The current landscape
Computation lithography has its root in lithography simulation, but has since
grown to encompass many technologies that are indispensable for IC development.
These include, among many others, the computation of partially coherent
imaging and resist development modeling. This “virtual world,” however, can
be divided into two categories: tools with sensible specifications and
performance meeting the targets (the “virtual reality”),
and those that fall short of one or both criteria (the “virtual virtuality”).
Many technologies today still live in the second realm; our view of the
boundary today is shown in Figure 1 below [1]. ![]() Fig 1: The reality-virtuality space of computation lithography (not to scale) [1]. Inverse lithography
(1) Phase-shifting masksInverse lithography is a powerful technique for model-based optical proximity correction (OPC). We tackle the challenging scenario of designing an alternating phase-shifting mask using inverse lithography. In particular, we show that a simple initialization scheme can enhance the image robustness at a very moderate cost. An example is given in Figure 2 below [2].
Fig 2: [left] Aerial image without phase initialization; [right] Aerial image with phase initialization using our scheme [2]. (2) Manufacturing variabilityMany OPC designs assume a particular set of nominal conditions, but in reality, the manufacturing contains variabilities, such as focus and dose variations. We have devised several schemes to incorporate focus variation expicitly, and show that they generally outperform other methods over a range of focus errors. An example is given in Figure 3. Techniques we have developed include:
Fig 3: [left] Aerial image with defocus; [right] Aerial image with defocus, designed with our scheme [3]. Algorithm variabilityComputation lithography relies on algorithms. These algorithms exhibit variability that can be as much as 5% of the critical dimension for the 65-nm technology. Using hotspot analysis and fixing as an example, such variability can be addressed on the algorithm level via controlling and eliminating its root causes, and on the application level by setting specifications that are commensurate with both the limitations of the algorithms and the goals of the application [6].
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FundingThe work is supported in part by grants from the Research Grants Council of the Hong Kong Special Administrative Region, and by the Areas of Excellence project Theory, Modeling, and Simulation of Emerging Electronics. |