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Jun Wang

B.S., M.S. SJTU, Ph.D. HKU


Dept. of Electrical and Electronic Engineering, University of Hong Kong, Hong Kong

Email : junwang@eee.hku.hk
Tel.  : (852) 6273-5410 (Mobile)
        (852) 2859-2698 (office)
Office:
Rm 806, Chow Yei Ching
        building, HKU, Hong Kong






Education

 
Research background

I. Sep, 2000 to Nov, 2004:

Ph.D. Candidate in Department of Electrical & Electronic Engineering, the University of Hong Kong. My research interests include: low-cost ASIC process for the sub-100nm optical technology nodes, optical lithography, design for manufacturability (DFM), design and process integration (DPI) for microelectronics manufacturing, resolution enhancement techniques (RET),  ASIC design, and RFIC performance analysis. Parts of my work include:

  1. Develop a low-cost ASIC process for the sub-100nm optical technology nodes. I focus on the application of RET-driven gridded layout on ASIC design. The layout strategies and lithographic approaches for gridded layout are presented in my study. By applying gridded-layout on the contact and poly-silicon layers using template lithography, a 70nm standard cell library can be reached by a 193nm technology, while the manufacturing cost is kept at the same level of the current 130nm node. There is no extra non-reusable mask required and only double exposures are used for the two layers. There is also no highly-optimized RETs (such as complex OPC) required

    Two U.S. patents (rectangular contact lithography and multiple-exposure lithography for circuit performance improvement) are applied about the new lithography approaches for the regularly-placed contacts in standard cells. Furthermore, with the layout methodology I proposed in my study, the current standard cell libraries can be easily migrated into the new gridded-layout 70nm node. This makes it convenient for customers to adopt the new process. 

  2. RFIC performance analysis. Research the performance of on-chip CMOS wireless transceivers, especially the mismatch and nonlinear distortion effects of balanced mixer in wireless transceivers.

  3. Automatic design flow for digital VLSI.

II. Sep, 1997 to Mar, 2000:

Graduate student in the Department of Electronic Engineering at Shanghai Jiao Tong University. Parts of my works include:

1.   Took part in the project, "Further Study of Electrical Performance Problems of Interconnection and Packaging for High-Speed Microelectronic Systems," which was supported by Natural Science Foundation, China. My interests include :

(1)    Transient simulation of high speed IC, and

(2)    Model interconnects/transmission lines in VLSI and Multi-Chips Modules (MCM).

2.   EDA programming. Design a CAD software for time domain circuit analysis and make an open interface in the software as an access for new models of circuit devices.

3.   VLSI model reduction for CAD applications.  Research reduction of large-scale linear RLC multi-port networks, presenting a new approach which use Block Arnoldi and transmission from s-domain to z-domain to get the time domain recursive macro-model from the original RLC linear multi-port network.


III. 1996 to Jul 1997:

Undergraduate student in the Department of Electronic Engineering, Shanghai Jiao Tong University.  Majored in Communication Techniques. Parts of my works include:

1.   Wireless transmitter design, and

2.   Research of intelligent Integrated Routing Systems in Building, and

3.   PC games development.

 

U.S. Patents

  1. Jun Wang and Alfred K. Wong, and Edmund Y. Lam, "Rectangular contacts lithography for circuits performance improvement," U. S. patent application No. 60/546,948, Feb, 2004.
  2. Jun Wang, Alfred K. Wong, "Multiple exposure method for circuits performance improvement," U. S. patent application No. 10/787,169, Feb, 2003.

 

Publications:

  Academic Journals:
  1. Jun Wang, Alfred K. Wong, and Edmund Y. Lam, "Standard cell design with RET-driven regularly-placed contacts and gates," SPIE Journal of Microlithography, Microfabrication and Microsystems, vol. 4, no.1, Jan, 2005.
  2. Jun Wang, Alfred K. Wong, and Edmund Y. Lam, "Standard cell layout with contacts on a grid," IEEE Trans. on Semiconductor Manufacturing, vol. 17, no. 3, pp.375-383, Aug. 2004.
  3. Jun Wang and Alfred K. Wong, "Designing ASICs with contacts on a grid," Microlithography World, Vol. 12 Issue 3, Aug, 2003.
  4. Q. W. Xu, Z. F. Li, Jun Wang, and J. F. Mao, "Transient analysis of lossy interconnects by modified method of characteristics", IEEE Trans. on Circuits and System, part I, vol.47, No.3, pp363-375, Mar. 2000.
  5. Jun Wang and Z. F. Li, "Programming recursive algorithm for transient simulation of interconnects in high speed VLSI," Journal of Shanghai Jiao Tong University, vol.33, No.1, pp.7-11. Jan. 1999.
  6. Q. W. Xu, Z. F. Li, Jun Wang, and J. F. Mao "Modeling of Transmission Lines by the Differential Quadrature Mothod", IEEE Microwave and Guided Wave Letters, vol.9, No.4, pp.145-147, Apr. 1999
  7. Q. W. Xu, Z. F. Li, and Jun Wang, "Recursive algorithm for the transient analysis for lossy transmission line", IEE Electronics Letters, vol.34, No.6, pp572-573, Mar. 1998.
  8. Q. W. Xu, Z. F. Li, and Jun Wang, "Transient simulation of lossy interconnects in VLSI by a recursive algorithm", International Journal of Electronics, vol.85, No.2, pp153-164, Aug. 1998.

  Conference proceedings:
  1. Jun Wang, Alfred K. Wong, and Edmund Y. Lam, "Performance optimization for gridded-layout standard cells," in 24th Annual BACUS Symposium on Photomask Technology, Proceeding of  SPIE, No. 5567,  Wolfgang Staud and J. Tracy Weed, ed., pp107-118, September 2004.
  2. Jun Wang, Alfred K. Wong, and Edmund Y. Lam, "Standard cell design with regularly-placed contacts and gates," in SPIE Design and Process Integration for Microelectronics Manufacturing III, Lars W. Liebmann, ed., Proceeding of  SPIE, No. 5379, pp. 55-66, Feb, 2004.
  3. Jun Wang, Alfred K. Wong, and Edmund Y. Lam, "Standard cell layout with grid-placed contacts," Proceeding of RIUPEEEC, Aug, 2003.
  4. Jun Wang and Alfred K. Wong, "Effects of grid-placed contacts on circuits performance," in SPIE Cost and Performance in Integrated Circuits, Alfred K. Wong, ed., Proceeding of  SPIE, No.5043, pp. 134-141, Feb, 2003.
  5. Jun Wang and Alfred K. Wong, "A study of on theoretical representation of inter-modulation in CMOS balanced mixers," Proceeding of IEEE Electron Devices Meeting, pp. 107-110, Jun, 2002.
  6. Jun Wang and Alfred K. Wong, "Effects of mismatch on CMOS double-balanced mixers: a theoretical analysis," Proceeding of IEEE Electron Devices Meeting, pp. 85-88, Jun, 2001.


Academic Awards

 

Others 



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