ELEC3612: VLSI Design Principles

Final exam on 12 May 2012 (Sat) 9.30am-12.00noon (2.5hrs) at Rm 141 Main Bldg.

• Announcement
• Basic course info
• Course description
• Lecture notes
• Homework
• Related articles and demos

Announcement

• [30 Apr] HW3 solution out. You may collect your marked HW3 from TA by end of this week.
• [12 Apr] HW3 out, due on 26 Apr (viz. final lesson). Next week is the FYP week of HKUEEE and there's NO class on 16 & 19 Apr.
• [30 Mar] Lectures 10 & 11 out.
• [27 Mar] Lecture 9 out.
• [21 Mar] Lecture 8 out. HW2 also out, which's simply Q3 of the 2010 Exam paper with due day on 5 April (Thu).
• [15 Mar] Lecture 7 posted.
• [09 Mar] Lecture 6 out. Those who haven't started to work on project, please start NOW or you may run out of time unnoticeably!
• [24 Feb] Lecture 5 out.
• [19 Feb] The long-waited HW1 out, due on 1 Mar (Thu). The "cancellation" of class on 27 Feb is cancelled due to a re-scheduling of my appointment, therefore NORMAL class on 27 Feb.
• [14 Feb] Lecture 4 posted. The class on 27 Feb (Mon) is cancelled, with a make-up class in the same slot on 5 Mar (Mon), whose venue would be confirmed later.
• [09 Feb] Lecture 3 posted.
• [07 Feb] A change of classroom on Monday to Main Bldg Room 141 (MB141) would be effective from 13 Feb onwards. The room on Thur remains unchanged.
• [30 Jan] Verilog tutorial + project details on 2 Feb (coming Thu) at CYC806 while I'm out of town from Tue-Fri this week. A Verilog basics document is posted below, too.
• [26 Jan] Happy Chinese New Year! For those who missed the first two lectures, please catch up hard. Lecture 2 posted and Thu of the coming week (2 Feb) would be a Verilog+Project tutorial class in CYC806 by the TA, ZHANG Yang, while I am out of town for a conference trip.
• [11 Jan] Lecture 1 posted, please open with the password I sent you via email. See you on 16 Jan!

Basic course information

Office Hours: By email appointment.

Course web page: up to date information, all lecture notes, homework assignments, and other important stuff will be found at http://www.eee.hku.hk/~nwong/elec3612/. It is your responsibility to check this webpage frequently and note the information available here!

Instructor: Ngai Wong, CYC 720, 2859-1914, nwong@eee.hku.hk

Remarks:

Mr. ZHANG Yang, an experienced IC designer and the TA of this course, will be teaching you Verilog (for digital IC design) and be responsible for an extended project which makes up most of the marks besides final exam. He is sitting in CYC806 and can be reached by yzhang@eee.hku.hk.

References:

Textbooks aren't necessary (but the first reference is a keeper if you like). Your attendance + notes should be adequate for examination. Below is a list of commonly used references, I have only flipped through a few, though.

• N. H. E. Weste & D. Harris, "CMOS VLSI Design: A Circuits and Systems Perspective", Addison-Wesley.
• Charles H. Roth, "Fundamentals of Logic Design", PWS.
• J. F. Wakerly, "Digital Design Principles & Practices", Pearson.
• N. Balabanian & B. Carlson, "Digital Logic Design Principles", Wiley.
• Brian Holdsworth, "Digital Logic Design", Butterworth-Heinemann Ltd.
• J. M. Rabaey, A. Chandrakasan and B. Nikolic, "Digital Integrated Circuits: A Design Perspective", Prentice Hall.
• Keshab K. Parhi, "VLSI Digital Signal Processing Systems", John Wiley & Sons.
• Randy H. Katz, "Contemporary Logic Design", Benjamin Cummings.

• Project + Assignments 50%, Final 50%

Prerequisites: ((ELEC1302 Electronic materials and devices) or (ELEC1614 Electronic devices and circuits)) and (interests in IC design)

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Course description

To give a detailed treatment on the principles and methods for designing large-scale digital integrated circuits.

Calendar Entry:

Technology issues, custom and semi-custom design, gate array and standard cell approach, programmable logic arrays, hierarchical design methodologies, design verification, automatic circuit/system synthesis, silicon compilation, design for testability.

Calendar as in Jan (tentative, subject to change upon your feedbacks)

Theories (teaching order may vary)

• High-level (rather than solid-state) CMOS logic circuits
• Transistor theory
• Circuit families
• Review of combinational logics and finite state machine
• Logical effort
• Finite State Machine
• Datapath
• Memory
• Simple CMOS analog blocks
• Design for testability
• Basic CMOS analog circuits etc.

Hands-on

• Hardware description language (HDL)
• Simulation techniques
• Programmable logic devices

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Downloads

1. Lecture 1: Introduction (4-page) (Updated: 11 Jan)
2. Lecture 2: Circuits & Layout (4-page) (Updated: 26 Jan)
3. Verilog basics (Updated: 30 Jan)
4. Lecture 3: MOS Theory (4-page) (Updated: 09 Feb)
5. Lecture 4: DC & Transient Responses (4-page) (Updated: 14 Feb)
6. Lecture 5: Logical Effort (4-page) (Updated: 24 Feb)
7. Lecture 6: More Logics (4-page) (Updated: 09 Mar)
8. Lecture 7: RAM and State Machine (4-page) (Updated: 15 Mar)
9. Lecture 8: Adders (4-page) (Updated: 21 Mar)
10. Lecture 9: Testing (4-page) (Updated: 27 Mar)
11. Lecture 10: CMOS Amplifiers (4-page) (Updated: 30 Mar)
12. Lecture 11: Basic Analog Circuits (4-page) (Updated: 30 Mar)

Homework/Projects

1. Homework 1 (Due: 01 Mar, Thu)
2. Homework 2: Q3 of 2010 Exam (Due: 05 Apr, Thu)
3. Homework 3 (Due: 26 Apr, Thu) Solution (Updated: 30 Apr)

Related sites/articles/demos

1. Webpage of the first reference. Our set of notes follows largely from it.
2. CAD page managed by Yang.

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Last updated: 30 Apr 2012