The role of 2D materials in fusion with silicon ICs
03 Mar, 2021 (Wed)Time:
10:00 am - 11:30 amWebinar Link:
SpeakerProf. Peng Zhou
Vice Dean of School of Microelectronics Fudan University
As the feature size of silicon-based integrated circuits (ICs) approaches the physical limit, short-channel effects appear, gate control attenuates, and leakage current increases, which seriously affects transistor performance and causes chip failure . Due to the inherent thickness of bulk silicon, the physical area cannot be further reduced, which restricts the area efficiency of silicon-based ICs . In addition, the speed mismatch between memory readout and logic operation , and the separation of memory and computing units together form the memory wall bottleneck in silicon-based ICs. With unique characteristics, including no dangling bond surface, atomic-level thickness, abundant adjustable energy bands, excellent optical electrostatic properties etc. , two-dimensional (2D) materials have the potential to enhance gate control, reduce leakage, improve energy and area efficiency, and realize the integration of perception, memory, and computing. This report discusses the roadmap for the fusion of 2D materials and silicon ICs, including alleviating the problems faced by silicon ICs from the application of 2D materials in gate-all-around, memory, and logic transistors, and enabling the creation of an all-in-one sensing, memory, and computing system. Finally, it provides an outlook on the challenges and promising paths to fusing 2D materials with silicon ICs for large-scale applications.
Registration Required: https://cutt.ly/flvicqD
Further Information: https://r10.ieee.org/hk-edssc/
Biography of the speaker:
Peng Zhou is a full professor at the State Key Laboratory of ASIC and system, School of Microelectronics, Fudan University, China. He received his B.S. (2000) and Ph.D. (2005) degrees in physics from Fudan University, China. Professor Zhou interests in novel high-efficiency and low-power electronic devices based on layered materials, focusing on the application to memory, synaptic electronics, and neuromorphic systems. His invention of the new flash memory featuring concurrent high-program speed and non-volatility gives rise to high area-efficiency single-transistor logic and in-situ memory, high-performance storage, and chips enabling high-efficiency algorithms. He has published more than 200 technical papers including those appearing on Nature Nanotechnology, Nature Electronics, Nature Communications, Advanced Materials, IEEE IEDM, and IEEE EDL.
OrganizerProf. Wallace C.H. Choy
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