N3XT: AI Chips with 1,000× Improvement of Computing Energy Efficiency
Date:
27 Apr, 2020 (Mon)
Time:
10:00 am - 11:30 am
Webinar Link:
https://bit.ly/2V7JY9T

Add to your calendar: iCal, Google Calendar

HKU Campus Map


Speaker

Prof. Philip Wong,
Willard R. and Inez Kerr Bell Professor
Department of Electrical Engineering
Stanford University

Abstract

The path for IC technology development going forward is no longer a straight line. The need for out-of-the-box solutions ushers in a golden age of innovation.

A scalable, fast, and energy-efficient computation platform that may provide another 1,000× improvement in computing energy efficiency (energy-execution time product) will have massive on-chip memory co-located with highly energy-efficient computing logic, enabled by 3D integration (e.g., monolithic) with ultra-dense and fine-grained connectivity. There will be multiple layers of memories interleaved with computing logic, sensors, and application-specific devices. We call this technology platform N3XT, Nano-engineered Computing Systems Technology. N3XT will support conventional computing architectures as well as computation methods that embrace sparsity, stochasticity, and device variability, including those that are neuromorphic and learning-based.

In this seminar, Professor Wong will give an overview of the memory, logic, and process technology innovations in the research pipeline today for realizing the N3XT vision.

 

Biography of the speaker:

H.-S. Philip Wong is the Willard R. and Inez Kerr Bell Professor in the School of Engineering at Stanford University. In 2018, he was on leave from Stanford and was the Vice President of Corporate Research at TSMC, the largest semiconductor foundry in the world. Since 2020, he has been the Chief Scientist of TSMC. He joined Stanford University as a Professor of Electrical Engineering in September 2004. From 1988 to 2004, he was with the IBM T.J. Watson Research Center.

He is a Fellow of the IEEE and received the IEEE Electron Devices Society J.J. Ebers Award. He served as the Editor-in-Chief of the IEEE Transactions on Nanotechnology (2005 – 2006), sub-committee Chair of the ISSCC (2003 – 2004), General Chair of the IEDM (2007), and is currently the Chair of the IEEE Executive Committee of the Symposia of VLSI Technology and Circuits. He received an honorary doctorate degree from Institut Polytechnique de Grenoble, France. Professor Wong and his students have won best paper awards at premier conferences such as the International Solid-State Circuits Conference (ISSCC) and Symposia on VLSI. He is the faculty director of the Stanford Non-Volatile Memory Technology Research Initiative (NMTRI), and is the founding Faculty Co-Director of the Stanford SystemX Alliance – an industrial affiliate program focused on building systems.

All are welcome!


Organizer

Dr. N Wong & Co-Organizer with IEEE ED/SSC Hong Kong Joint Chapter

Most seminars are open to the general public, free of charge, unless otherwise stated. Registration is not required. Arrangement for car parking facilities on campus please contact us for details.

For enquiries, please contact:
Department of Electrical and Electronic Engineering,
Room 601, Chow Yei Ching Building,
Pokfulam Road, Hong Kong
Tel: (852) 3917 7093
Email: seminar@eee.hku.hk