Publications
Book Chapter
- H. K.-H. So and C. Liu, "FPGA Overlays," FPGAs for Software Programmers, D. Koch, F. Hannig, and D. Ziener, Ed. 2016, pp. 327-343. [doi>10.1007/978-3-319-26408-0_16]
Journal
- T. Zeng, H. K.-H. So, and E. Y. Lam, "RedCap: residual encoder-decoder capsule network for holographic image reconstruction," Opt. Express, vol. 28, no. 4, pp. 4876--4887, Feb, 2020. [doi>10.1364/OE.383350]
- S. V. Stassen, D. M. D. Siu, K. C. M. Lee, J. W. K. Ho, H. K. H. So, and K. K. Tsia, "PARC: ultrafast and accurate clustering of phenotypic data of millions of single cells," Bioinformatics, Jan., 2020. [doi>10.1093/bioinformatics/btaa042]
- N. Engelhardt and H. K.-H. So, "GraVF-M: Graph Processing System Generation for Multi-FPGA Platforms," ACM Trans. Reconfigurable Technol. Syst., vol. 12, no. 4, pp. 21:1--21:28, November, 2019. [doi>10.1145/3357596]
- N. Meng, H. K.-H. So, X. Sun, and E. Lam, "High-dimensional Dense Residual Convolutional Neural Network for Light Field Reconstruction," IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. ( Early Access ), pp. 1-14, Oct, 2019. [doi>10.1109/TPAMI.2019.2945027]
- R. Shi, J. S. J. Wong, E. Y. Lam, K. K. Tsia, and H. K.-H. So, "A Real-Time Coprime Line Scan Super-Resolution System for Ultra-Fast Microscopy," IEEE Transactions on Biomedical Circuits and Systems, vol. 13, no. 4, pp. 781-792, Aug, 2019. [doi>10.1109/TBCAS.2019.2914946]
- M. K. Jaiswal and H. K.-H. So, "PACoGen: A Hardware Posit Arithmetic Core Generator," IEEE Access, vol. 7, pp. 74586-74601, Jun, 2019. [doi>10.1109/ACCESS.2019.2920936]
- R. Shi, J. Liu, H. K.-H. So, S. Wang, and Y. Liang, "E-LSTM: Efficient Inference of Sparse LSTM on Embedded Heterogeneous System," in Proceedings of the 56th Annual Design Automation Conference 2019, pp. 182:1--182:6, Jun, 2019. [doi>10.1145/3316781.3317813]
- Z. Ren, H. K.-H. So, and E. Y. Lam, "Fringe Pattern Improvement and Super-Resolution Using Deep Learning in Digital Holography," IEEE Transactions on Industrial Informatics, vol. 15, no. 11, pp. 6179-6186, Nov, 2019. [doi>10.1109/TII.2019.2913853]
- K. C. M. Lee, M. Wang, K. S. E. Cheah, G. C. F. Chan, H. K. H. So, K. K. Y. Wong, and K. K. Tsia, "Quantitative Phase Imaging Flow Cytometry for Ultra-Large-Scale Single-Cell Biophysical Phenotyping," Cytometry Part A, vol. 95, no. 5, pp. 510-520, Apr, 2019. [doi>10.1002/cyto.a.23765]
- T. Zeng, H. K.-H. So, and E. Y. Lam, "Computational image speckle suppression using block matching and machine learning," Appl. Opt., vol. 58, no. 7, pp. B39--B45, Mar, 2019. [doi>10.1364/AO.58.000B39]
- R. Shi, J. S. J. Wong, and H. K.-H. So, "High-Throughput Line Buffer Microarchitecture for Arbitrary Sized Streaming Image Processing," Journal of Imaging, vol. 5, no. 3, Mar, 2019. [doi>10.3390/jimaging5030034]
- M. K. Jaiswal and H. K.-H. So, "Design of quadruple precision multiplier architectures with SIMD single and double precision support," Integration, vol. 65, pp. 163 - 174, Mar, 2019. [doi>https://doi.org/10.1016/j.vlsi.2018.12.002]
- N. Meng, X. Sun, H. K.-H. So, and E. Y. Lam, "Computational Light Field Generation Using Deep Nonparametric Bayesian Learning," IEEE Access, vol. 7, pp. 24990-25000, Feb, 2019. [doi>10.1109/ACCESS.2019.2900153]
- K. C. M. Lee, A. K. S. Lau, A. H. L. Tang, M. Wang, A. T. Y. Mok, B. M. F. Chung, W. Yan, H. C. Shum, K. S. E. Cheah, G. C. F. Chan, H. K. H. So, K. K. Y. Wong, and K. K. Tsia, "Multi-ATOM: Ultrahigh-throughput single-cell quantitative phase imaging with subcellular resolution," Journal of Biophotonics, pp. e201800479, Feb, 2019. [doi>10.1002/jbio.201800479]
- N. Meng, E. Lam, K. K. M. Tsia, and H. K.-H. So, "Large-scale Multi-class Image-based Cell Classification with Deep Learning," IEEE Journal of Biomedical and Health Informatics, vol. 23, no. 5, pp. 2091-2098, Sep, 2019. [doi>10.1109/JBHI.2018.2878878]
- W. Zhao, J. Q. Lin, S. C. Chan, and H. K.-H. So, "A Division-Free and Variable-Regularized LMS-Based Generalized Sidelobe Canceller for Adaptive Beamforming and Its Efficient Hardware Realization," IEEE Access, vol. 6, pp. 64470-64485, 2018. [doi>10.1109/ACCESS.2018.2875409]
- M. K. Jaiswal and H. K.-H. So, "An Unified Architecture for Single, Double, Double-Extended, and Quadruple Precision Division," Circuits, Systems, and Signal Processing, vol. 37, no. 1, pp. 383--407, Jan, 2018. [doi>10.1007/s00034-017-0559-9] [pdf]
- P. H. W. Leong, H. Amano, J. Anderson, K. Bertels, J. M. P. Cardoso, O. Diessel, G. Gogniat, M. Hutton, J. Lee, W. Luk, P. Lysaght, M. Platzner, V. Prasanna, T. Rissa, C. Silvano, H. K. H. So, and Y. Wang, "The First 25 Years of the FPL Conference --- Significant Papers," ACM Transactions on Reconfigurable Technology and Systems, Volume 10 Issue 2, April 2017. [doi>10.1145/2996468]
- A. C. S. Chan, H.-C. Ng, S. C. V. Bogaraju, H. K. H. So, E. Y. Lam, and K. K. Tsia, "All-passive pixel super-resolution of time-stretch imaging," Scientific Reports, vol. 7, no. 44608, Mar, 2017. [doi>10.1038/srep44608]
- X. Sun, N. H. C. Yung, E. Y. Lam, and H. K. H. So, "Computationally Efficient Hyperspectral Data Learning Based on the Doubly Stochastic Dirichlet Process," IEEE Transactions on Geoscience and Remote Sensing, vol. 55, no. 1, pp. 363-374, Jan, 2017. [doi>10.1109/TGRS.2016.2606575]
- C. Y. Lin, Z. Jiang, C. Fu, H. K.-H. So, and H. Yang, "FPGA High-level Synthesis Versus Overlay: Comparisons on Computation Kernels," SIGARCH Comput. Archit. News, vol. 44, no. 4, pp. 92--97, January, 2017. [doi>10.1145/3039902.3039919]
- Q. T. K. Lai, K. C. M. Lee, A. H. L. Tang, K. K. Y. Wong, H. K. H. So, and K. K. Tsia, "High-throughput time-stretch imaging flow cytometry for multi-class classification of phytoplankton," Opt. Express, vol. 24, no. 25, pp. 28170--28184, Dec, 2016. [doi>10.1364/OE.24.028170]
- M. K. Jaiswal and H. K.-H. So, "Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 2, pp. 386-398, Feb, 2017. [doi>10.1109/TCSI.2016.2607227] [pdf]
- M. K. Jaiswal, B. S. C. Varma, H. K. H. So, M. Balakrishnan, K. Paul, and R. C. C. Cheung, "Configurable Architectures for Multi-Mode Floating Point Adders," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 8, pp. 2079-2090, Aug, 2015. [doi>10.1109/TCSI.2015.2452351] [pdf]
- C. Y. Lin, N. Wong, and H. K.-H. So, "Design space exploration for sparse matrix-matrix multiplication on FPGAs," International Journal of Circuit Theory and Applications, vol. 41, no. 2, pp. 205--219, 2013. [doi>10.1002/cta.796]
- C. Y. Lin and H. K.-H. So, "Energy-efficient Dataflow Computations on FPGAs Using Application-specific Coarse-grain Architecture Synthesis," SIGARCH Comput. Archit. News, vol. 40, no. 5, pp. 58--63, March, 2012. [doi>10.1145/2460216.2460227]
- J. Chen, B. Y. S. Yiu, B. K. Hamilton, A. C. H. Yu, and H. K.-H. So, "Design Space Exploration of Adaptive Beamforming Acceleration for Bedside and Portable Medical Ultrasound Imaging," SIGARCH Comput. Archit. News, vol. 39, no. 4, pp. 20--25, December, 2011. [doi>10.1145/2082156.2082162]
- H. K.-H. So, J. Chen, B. Yiu, and A. Yu, "Medical Ultrasound Imaging: To GPU or Not to GPU?," Micro, IEEE, vol. 31, no. 5, pp. 54 -65, sep, 2011. [doi>10.1109/MM.2011.65]
- C.-C. Tsang and H. K.-H. So, "Dynamic Power Reduction of FPGA-based Reconfigurable Computers Using Precomputation," SIGARCH Comput. Archit. News, vol. 38, no. 4, pp. 87--92, January, 2011. [doi>10.1145/1926367.1926382]
- C.-W. Ng, N. Wong, H. K.-H. So, and T.-S. Ng, "On IIR-based bit-stream multipliers," International Journal of Circuit Theory and Applications, vol. 39, no. 2, pp. 149--158, 2011. [doi>10.1002/cta.623]
- S. H. M. Kwok, H. K. H. So, E. Y. Lam, and K. S. Lui, "Zero-configuration identity-based IP network encryptor," IEEE Transactions on Consumer Electronics, vol. 56, no. 2, pp. 540-546, May, 2010. [doi>10.1109/TCE.2010.5505967]
- H. K.-H. So and R. Brodersen, "A Unified Hardware/Software Runtime Environment for FPGA-Based Reconfigurable Computers using BORPH," ACM Transactions on Embedded Computing Systems (TECS), Volume 7, Issue 2, Feb, 2008, New York, NY, USA. [pdf] [BibTex]
Peer-Reviewed Conferences
- C. W. H. Chan, P. H. W. Leong, and H. K.-H. So, "Vision Guided Crop Detection in Field Robots using FPGA-based Reconfigurable Computers," in FoodCAS 2020, May., 2020.
- R. Shi, J. Liu, H. K.-H. So, S. Wang, and Y. Liang, "E-LSTM: Efficient Inference of Sparse LSTM on Embedded Heterogeneous System," in Proceedings of the 56th Annual Design Automation Conference 2019, pp. 182:1--182:6, Jun, 2019. [doi>10.1145/3316781.3317813]
- V. W. L. Tam, C. K. Chui, H. K. So, N. T. Khaing, A. Kong, and S. Roy, "Urban Farming in Myanmar: An Experiential Learning Project for Engineering and Science Students from Hong Kong and Myanmar," in 2018 IEEE International Conference on Teaching, Assessment, and Learning for Engineering (TALE), pp. 1185-1188, Dec, 2018. [doi>10.1109/TALE.2018.8615341]
- N. Engerhardt, D. C.-H. Hung, and H. K.-H. So, "Performance-Driven System Generation for Distributed Vertex-Centric Graph Processing on Multi-FPGA Systems," in 2018 28th International Conference on Field Programmable Logic and Applications (FPL), pp. 215-2153, Aug, 2018. [doi>10.1109/FPL.2018.00043] [pdf]
- M. K. Jaiswal and H. K.-K. So, "Architecture Generator for Type-3 Unum Posit Adder/Subtractor," in 2018 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, May, 2018. [doi>10.1109/ISCAS.2018.8351142]
- K. C. M. Lee, M. Wang, H. K. H. So, and K. K. Tsia, "Ultra-large-scale single-cell quantitative phase imaging," in Biophotonics Congress: Biomedical Optics Congress 2018 (Microscopy/Translational/Brain/OTS), pp. MF3A.4, Apr, 2018. [doi>10.1364/MICROSCOPY.2018.MF3A.4]
- M. K. Jaiswal and H. K.-H. So, "Universal number posit arithmetic generator on FPGA," in 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 1159-1162, March, 2018. [doi>10.23919/DATE.2018.8342187]
- E. Y. Lam, N. Meng, and H. K. H. So, "Deep convolutional neural network for single-cell image analysis (Conference Presentation)," Proc. SPIE, vol. 10505, Mar, 2018. [doi>10.1117/12.2295469]
- S. M. H. Ho and H. K. H. So, "NnCore: A parameterized non-linear function generator for machine learning applications in FPGAs," in 2017 International Conference on Field Programmable Technology (ICFPT), pp. 160-167, Dec, 2017. [doi>10.1109/FPT.2017.8280134]
- J. S. J. Wong, R. Shi, M. Wang, and H. K. H. So, "Ultra-low latency continuous block-parallel stream windowing using FPGA on-chip memory," in 2017 International Conference on Field Programmable Technology (ICFPT), pp. 56-63, Dec, 2017. [doi>10.1109/FPT.2017.8280121]
- R. Shi, A. C.S. Chan, E. Y. Lam, and H. K.-H. So, "Image super-resolution for ultrafast optical time-stretch imaging," in 24th Congress of the International Commission for Optics, pp. W1F-08, August 2017.
- N. Engelhardt and H. K.-H. So, "Towards Flexible Automatic Generation of Graph Processing Gateware," in Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, pp. 5:1--5:6, Jun, 2017. [doi>10.1145/3120895.3120896] [pdf]
- C. K. Chui, H. K.-H. So, and N. T. Khaing, "Wastewater treatment in Myanmar: A multidisciplinary learning experience for engineering and science students from two countries," in 2017 ASEE International Forum, June, 2017. [https://peer.asee.org/29311]
- N. Meng, H. K. H. So, and E. Y. Lam, "Computational single-cell classification using deep learning on bright-field and phase images," in 2017 Fifteenth IAPR International Conference on Machine Vision Applications (MVA), pp. 190-193, May, 2017. [doi>10.23919/MVA.2017.7986833]
- S. M. H. Ho, C. H. D. Hung, H. C. Ng, M. Wang, and H. K. H. So, "A Parameterizable Activation Function Generator for FPGA-Based Neural Network Applications," in 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 84-84, April, 2017. [doi>10.1109/FCCM.2017.40]
- M. K. Jaiswal and H. K. H. So, "DSP48E efficient floating point multiplier architectures on FPGA," in 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), pp. 1-6, Jan, 2017. [doi>10.1109/ICVD.2017.7913322]
- M. Wang, H. C. Ng, B. M. F. Chung, B. S. C. Varma, M. K. Jaiswal, K. K. Tsia, H. C. Shum, and H. K. H. So, "Real-time object detection and classification for high-speed asymmetric-detection time-stretch optical microscopy on FPGA," in 2016 International Conference on Field-Programmable Technology (FPT), pp. 261-264, Dec, 2016. [doi>10.1109/FPT.2016.7929548]
- S. M. H. Ho, M. Wang, H. C. Ng, and H. K. H. So, "Towards FPGA-assisted Spark: An SVM training acceleration case study," in 2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 1-6, Nov, 2016. [doi>10.1109/ReConFig.2016.7857194]
- H. C. Ng, M. Wang, B. M. F. Chung, B. S. C. Varma, M. K. Jaiswal, S. M. H. Ho, K. K. Tsia, H. C. Shum, and H. K. H. So, "High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platform," in 2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 1-6, Nov, 2016. [doi>10.1109/ReConFig.2016.7857175]
- M. K. Jaiswal and H. K.-H. So, "Dual-Mode Double Precision Division Architecture," in 59th International Midwest Symposium on Circuits and Systems (MWSCAS2016), Oct, 2016. [doi>10.1109/MWSCAS.2016.7869984]
- N. Engelhardt and H. K. H. So, "GraVF: A vertex-centric distributed graph processing framework on FPGAs," in 2016 26th International Conference on Field Programmable Logic and Applications (FPL), pp. 1-4, Aug, 2016. [doi>10.1109/FPL.2016.7577360] [pdf] [BibTex]
- M. K. Jaiswal and H. K. H. So, "Architecture for quadruple precision floating point division with multi-precision support," in 2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 239-240, July, 2016. [doi>10.1109/ASAP.2016.7760807]
- M. K. Jaiswal and H. K. H. So, "Taylor Series Based Architecture for Quadruple Precision Floating Point Division," in 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 518-523, July, 2016. [doi>10.1109/ISVLSI.2016.10]
- X. Sun, N. Meng, Z. Xu, E. Y. Lam, and H. K. H. So, "Sparse Hierarchical Nonparametric Bayesian learning for light field representation and denoising," in 2016 International Joint Conference on Neural Networks (IJCNN), pp. 3272-3279, July, 2016. [doi>10.1109/IJCNN.2016.7727617]
- X. Sun, Z. Xu, N. Meng, E. Y. Lam, and H. K. H. So, "Data-driven light field depth estimation using deep Convolutional Neural Networks," in 2016 International Joint Conference on Neural Networks (IJCNN), pp. 367-374, July, 2016. [doi>10.1109/IJCNN.2016.7727222]
- N. Engelhardt and H. K.-H. So, "Vertex-centric Distributed Graph Processing on FPGA," in 7th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), PhD Forum, Jun, 2016.
- M. Wang and H. K.-H. So, "In-situ Object Detection and Classification on FPGA for Asymmetric-Detection Time-Stretch Optical Microscopy," in 7th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), PhD Forum, Jun, 2016.
- N. Engelhardt and H. K. H. So, "Vertex-Centric Graph Processing on FPGA," in 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 92-92, May, 2016. [doi>10.1109/FCCM.2016.31]
- X. Sun, N. H. C. Yung, E. Y. Lam, and H. K.-H. So, "Unsupervised tracking with a low computational cost using the doubly stochastic Dirichlet process mixture model," Electronic Imaging, vol. 2016, no. 14, pp. 1-8, Feb, 2016. [doi>doi:10.2352/ISSN.2470-1173.2016.14.IPMVA-381]
- H.-C. Ng, C. Liu, and H. K.-H. So, "A Soft Processor Overlay with Tightly-coupled FPGA Accelerator," in Overlay Architectures for FPGAs (OLAF), Second International Workshop on, Feb., 2016. [arXiv:1606.06483]
- B. Chung, H.-C. Ng, M. Wang, S. C. V. Bogaraju, A. H. C. Shum, H. K. H. So, and K. K. Tsia, "High-throughput microparticle screening by 1-$\mu$m time-stretch optofluidic imaging integrated with a field-programmable gate array platform," Conference on Lasers and Electro-Optics, pp. STh3G.4, 2016. [doi>10.1364/CLEO_SI.2016.STh3G.4]
- C. Liu, H. C. Ng, and H. K. H. So, "QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlay," in 2015 International Conference on Field Programmable Technology (FPT), pp. 56-63, Dec, 2015. [doi>10.1109/FPT.2015.7393130][pdf] [BibTex]
- J. Xie, X. Niu, A. K. S. Lau, K. K. Tsia, and H. K. H. So, "Accelerated cell imaging and classification on FPGAs for quantitative-phase asymmetric-detection time-stretch optical microscopy," in 2015 International Conference on Field Programmable Technology (FPT), pp. 1-8, Dec, 2015. [doi>10.1109/FPT.2015.7393123]
- Z. Ullah, M. K. Jaiswal, R. C. C. Cheung, and H. K. H. So, "UE-TCAM: An ultra efficient SRAM-based TCAM," in TENCON 2015 - 2015 IEEE Region 10 Conference, pp. 1-6, Nov, 2015. [doi>10.1109/TENCON.2015.7372837]
- M. K. Jaiswal and H. K. H. So, "Dual-mode double precision / two-parallel single precision floating point multiplier architecture," in 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 213-218, Oct, 2015. [doi>10.1109/VLSI-SoC.2015.7314418]
- C. Liu, H.-C. Ng, and H. K.-H. So, "Automatic Nested Loop Acceleration on FPGAs Using Soft CGRA Overlay," in FPGAs for Software Programmers (FSP), Second International Workshop on, Sep, 2015. [arXiv:1509.00042]
- M. K. Jaiswal, B. S. C. Varma, and H. K. H. So, "Architecture for Dual-Mode Quadruple Precision Floating Point Adder," in 2015 IEEE Computer Society Annual Symposium on VLSI, pp. 249-254, July, 2015. [doi>10.1109/ISVLSI.2015.70]
- B. K. Hamilton, M. Inggs, and H. K.-H. So, "Mixed-architecture process scheduling on tightly coupled reconfigurable computers," in Field Programmable Logic and Applications (FPL), 2014 24th International Conference on, pp. 1-4, Sep, 2014. [doi>10.1109/FPL.2014.6927421]
- Y.-M. Choi and H. K.-H. So, "Map-reduce processing of k-means algorithm with FPGA-accelerated computer cluster," in Application-specific Systems, Architectures and Processors (ASAP), 2014 IEEE 25th International Conference on, pp. 9-16, June, 2014. [doi>10.1109/ASAP.2014.6868624] [pdf] [BibTex]
- B. K. Hamilton, M. Inggs, and H. K. H. So, "Scheduling Mixed-Architecture Processes in Tightly Coupled FPGA-CPU Reconfigurable Computers," in 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines, pp. 240-240, May, 2014. [doi>10.1109/FCCM.2014.75]
- H.-C. Ng, Y.-M. Choi, and H. K.-H. So, "Direct virtual memory access from FPGA for high-productivity heterogeneous computing," in Field-Programmable Technology (FPT), 2013 International Conference on, pp. 458-461, Dec, 2013. [doi>10.1109/FPT.2013.6718414]
- C. Liu, C. L. Yu, and H. K. H. So, "A Soft Coarse-Grained Reconfigurable Array Based High-level Synthesis Methodology: Promoting Design Productivity and Exploring Extreme FPGA Frequency," in 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines, pp. 228-228, April, 2013. [doi>10.1109/FCCM.2013.21]
- J. Chen, A. C. H. Yu, and H. K. H. So, "Design considerations of real-time adaptive beamformer for medical ultrasound research using FPGA and GPU," in 2012 International Conference on Field-Programmable Technology, pp. 198-205, Dec, 2012. [doi>10.1109/FPT.2012.6412134]
- X. Changqing, W. Mei, W. Nan, Z. Chunyuan, and H. K. H. So, "Extending BORPH for shared memory reconfigurable computers," in 22nd International Conference on Field Programmable Logic and Applications (FPL), pp. 563-566, Aug, 2012. [doi>10.1109/FPL.2012.6339371]
- C. U. Lei, H. K.-H. So, E. Y. Lam, K. K. Y. Wong, R. Y. K. Kwok, and C. K. Y. Chan, "Teaching introductory electrical engineering: Project-based learning experience," in Proceedings of IEEE International Conference on Teaching, Assessment, and Learning for Engineering (TALE) 2012, pp. H1B-1-H1B-5, Aug, 2012. [doi>10.1109/TALE.2012.6360320]
- J. Chen, B. Y. S. Yiu, H. K.-H. So, and A. C. H. Yu, "Real-time GPU-based adaptive beamformer for high quality ultrasound imaging," in Ultrasonics Symposium (IUS), 2011 IEEE International, pp. 474-477, Oct, 2011. [doi>10.1109/ULTSYM.2011.0114]
- C. Y. Lin, H. K. H. So, and P. H. W. Leong, "A Model for Matrix Multiplication Performance on FPGAs," in 2011 21st International Conference on Field Programmable Logic and Applications, pp. 305-310, Sep, 2011. [doi>10.1109/FPL.2011.62]
- C. Y. Lin, H. K. H. So, and P. H. W. Leong, "A Model for Peak Matrix Performance on FPGAs," in 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, pp. 251-251, May, 2011. [doi>10.1109/FCCM.2011.51]
- C. Y. Lin, Z. Zhang, N. Wong, and H. K. H. So, "Design space exploration for sparse matrix-matrix multiplication on FPGAs," in 2010 International Conference on Field-Programmable Technology, pp. 369-372, Dec, 2010. [doi>10.1109/FPT.2010.5681425]
- H. K. H. So, S. H. M. Kwok, E. Y. Lam, and K. S. Lui, "Zero-Configuration Identity-Based Signcryption Scheme for Smart Grid," in 2010 First IEEE International Conference on Smart Grid Communications, pp. 321-326, Oct, 2010. [doi>10.1109/SMARTGRID.2010.5622061]
- B. K. Hamilton and H. K.-H. So, "BORPH: Operating system support on the NetFPGA platform," in 2nd North American NetFPGA Developers Workshop, Aug, 2010.
- C. Y. Lin, N. Wong, and H. K. H. So, "Automatic system architecture synthesis for FPGA-based reconfigurable computers," in 2009 International Conference on Field-Programmable Technology, pp. 475-476, Dec, 2009. [doi>10.1109/FPT.2009.5377691]
- C. C. Tsang and H. K. H. So, "Reducing dynamic power consumption in FPGAs using precomputation," in 2009 International Conference on Field-Programmable Technology, pp. 407-410, Dec, 2009. [doi>10.1109/FPT.2009.5377692]
- S. Lang, C. Y. Lin, J. Liu, N. Wong, and H. K.-H. So, "A comparison of SAR image speckle filters," in MIPPR 2009: Remote Sensing and GIS Data Processing and Other Applications, pp. 749804-749804-5, Oct, 2009. [doi>10.1117/12.830946]
- C. Y. Lin, N. Wong, and H. K. H. So, "Operation scheduling for FPGA-based reconfigurable computers," in 2009 International Conference on Field Programmable Logic and Applications, pp. 481-484, Aug, 2009. [doi>10.1109/FPL.2009.5272497]
- C. W. Ng, N. Wong, H. K. H. So, and T. S. Ng, "Quad-level bit-stream signal processing on FPGAs," in 2008 International Conference on Field-Programmable Technology, pp. 309-312, Dec, 2008. [doi>10.1109/FPT.2008.4762405]
- H. K.-H. So and R. Brodersen, "File System Access from Reconfigurable FPGA Hardware Processes in BORPH," in Proc. International Conference on Field Programmable Logic and Applications (FPL'08), pp.567-570, 8-10 Sep. 2008. [doi>10.1109/FPL.2008.4630010] [pdf]
- C.-W. Ng, N. Wong, H. K.-H. So and T. S. Ng, "Direct Sigma-Delta Modulated Signal Processing in FPGA," in Proc. International Conference on Field Programmable Logic and Applications (FPL'08), pp.475-478, 8-10 Sep. 2008. [doi>10.1109/FPL.2008.4629987] [pdf]
- H. K.-H. So and R. Brodersen, "Runtime Filesystem Support for Reconfigurable FPGA Hardware Processes in BORPH," Field-Programmable Custom Computing Machines, 2008. FCCM '08. 16th International Symposium on, pp.285-286, 14-15 April 2008. [doi>10.1109/FCCM.2008.7] [pdf]
- S. Mellers, B. Richards, H. K.-H. So, M. S. Mishra, K. Camera, P. A. Subrahmanyam, R. W. Brodersen, "Radio Testbeds Using BEE2," Signals, Systems and Computers, 2007. ACSSC 2007. Conference Record of the Forty-First Asilomar Conference on, 4-7 Nov. 2007, pp. 1991-1995. [doi>10.1109/ACSSC.2007.4487585] [pdf]
- D. Markovic, C. Chang, B. Richards, H. So, B. Nikolic and R. Brodersen, "ASIC Design and Verification in an FPGA Environment," In Proc. IEEE Custom Integrated Circuits Conference (CICC), Sep. 2007, pp. 737-740 [doi>10.1109/CICC.2007.4405836] [pdf]
- H. K.-H. So and R. W. Brodersen, "Improving Usability of FPGA-based Reconfigurable Computers Through Operating System Support," in Proceedings of 2006 International Conference on Field Programmable Logic and Applications (FPL), Aug. 2006, pp. 349-354. [doi>10.1109/FPL.2006.311236] [pdf]
- K. Camera, H. K.-H. So, R. Brodersen, "An Integrated Debugging Environment for Reprogrammable Hardware Systems," in AADEBUG'05: Proceedings of the Sixth International Symposium on Automated Analysis-Driven Debugging. New York, NY, USA: ACM Press, 2006, pp. 111-116. [doi>10.1145/1085130.1085145] [pdf]
- H. K.-H. So, A. Tkachenko and R. Brodersen, "A Unified Hardware/Software Runtime Environment for FPGA-based Reconfigurable Computers Using BORPH," in CODES+ISSS '06: Proceedings of the 4th international conference on hardware/software codesign and system synthesis. New York, NY, USA: ACM Press, 2006, pp. 259-264. [doi>10.1145/1176254.1176316] [pdf]
Conference Poster
- C. Y. Lin, N. Wong and H. K.-H. So, "Operation scheduling and architecture co-synthesis for energy-efficient dataflow computations on FPGAs," Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays, p.270, Feb., 2012. [doi: 10.1145/2145694.2145757]
- Y. Lin, Z. Zhang, N. Wong, H.K.-H. So, "Power-delay and energy-delay tradeoffs in sparse matrix-matrix multiplication on FPGAs," Fifth International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2010.
- C. Y. Lin, N. Wong and H. K.-H. So, "An Integer Linear Programming Model for Automated Matrix Operation Scheduling on FPGAs," Proceedings of the Seventeenth Annual IEEE Symposium on Field-Programmable Custom Computing Machine, Apr. 2009.
White Paper
- Parsons A., Werthimer D., Backer D., Bastian T., Bower G., Brisken W., Chen H., Deller A., Filiba T., Gary D., Greenhill L., Hawkins D., Jones G., Langston G., Lazio J., van Leeuwen J., Mitchell D., Manley J., Siemion A., So H.K.H., Whitney A., Woody D., Wright M. and Zarb-Adami K., "Digital Instrumentation for the Radio Astronomy Community," Astro2010: The Astronomy and Astrophysics Decadal Survey, National Research Council (NRC), The National Academy of Sciences, arXiv:0904.1181v1 [astro-ph.IM], Apr., 2009.
Patents
- Adam P. Donlin, Brandon J. Blodget, Paul M. Hartke, Patrick Lysaght, Hayden Kwok-Hay So, "Debugging using a virtual file system interface," US Patents US7890916 B1, 2011.