# Reconfigurable Computing

My main research interest is on FPGA-based reconfigurable computers (RCs). A reconfigurable computer take advantage of the reconfigurable fabrics, such as FPGAs, to adapt its architecture for each application, thereby delivering unparalleled performance when compared to conventional processor-based system. My research goal is to investigate in all aspects of RCs that will enable RCs to become main stream high-performance computing systems. The following list highlights my current research efforts:## FPGA Overlay

- R. Shi, Y. Ding, X. Wei, H. Li, H. Liu, H. K.-H. So, and C. Ding, "FTDL: A Tailored FPGA-Overlay for Deep Learning with High Scalability," in
*57th Design Automation Conference (DAC)*, Jul., 2020. - C. Liu, H. C. Ng, and H. K. H. So, "QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlay," in
*2015 International Conference on Field Programmable Technology (FPT)*, pp. 56-63, Dec, 2015. [doi>10.1109/FPT.2015.7393130][pdf] [BibTex] - C. Y. Lin and H. K.-H. So, "Energy-efficient Dataflow Computations on FPGAs Using Application-specific Coarse-grain Architecture Synthesis,"
*SIGARCH Comput. Archit. News*, vol. 40, no. 5, pp. 58--63, March, 2012. [doi>10.1145/2460216.2460227] - H. K.-H. So and C. Liu, "FPGA Overlays,"
*FPGAs for Software Programmers*, D. Koch, F. Hannig, and D. Ziener, Ed. 2016, pp. 327-343. [doi>10.1007/978-3-319-26408-0_16] - H.-C. Ng, C. Liu, and H. K.-H. So, "A Soft Processor Overlay with Tightly-coupled FPGA Accelerator," in
*Overlay Architectures for FPGAs (OLAF), Second International Workshop on*, Feb., 2016. [arXiv:1606.06483] - C. Liu, H.-C. Ng, and H. K.-H. So, "Automatic Nested Loop Acceleration on FPGAs Using Soft CGRA Overlay," in
*FPGAs for Software Programmers (FSP), Second International Workshop on*, Sep, 2015. [arXiv:1509.00042] - C. Y. Lin, N. Wong, and H. K. H. So, "Operation scheduling for FPGA-based reconfigurable computers," in
*2009 International Conference on Field Programmable Logic and Applications*, pp. 481-484, Aug, 2009. [doi>10.1109/FPL.2009.5272497]

## AI Hardware & Applications

- R. Shi, Y. Ding, X. Wei, H. Li, H. Liu, H. K.-H. So, and C. Ding, "FTDL: A Tailored FPGA-Overlay for Deep Learning with High Scalability," in
*57th Design Automation Conference (DAC)*, Jul., 2020. - R. Shi, P. Dong, T. Geng, Y. Ding, X. Ma, H. K.-H. So, M. Herbordt, A. Li, and Y. Wang, "CSB-RNN: A Faster-than-Realtime RNN Acceleration Framework with Compressed Structured Blocks," in
*International Conference on Supercomputing (ICS)*, Jun., 2020. - C. W. H. Chan, P. H. W. Leong, and H. K.-H. So, "Vision Guided Crop Detection in Field Robots using FPGA-based Reconfigurable Computers," in
*FoodCAS*, May., 2020. - J. Liu, Z. Xu, R. Shi, R. C. C. Cheung, and H. K.-H. So, "Dynamic Sparse Training: Find Efficient Sparse Network From Scratch With Trainable Masked Layers," in
*Eighth International Conference on Learning Representations (ICLR)*, Apr., 2020. - R. Shi, Y. Ding, X. Wei, H. Liu, H. So, and C. Ding, "FTDL: An FPGA-Tailored Architecture for Deep Learning Systems," in
*The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays*, pp. 320, Feb., 2020. [doi>10.1145/3373087.3375384] - R. Shi, J. Liu, H. K.-H. So, S. Wang, and Y. Liang, "E-LSTM: Efficient Inference of Sparse LSTM on Embedded Heterogeneous System," in
*Proceedings of the 56th Annual Design Automation Conference 2019*, pp. 182:1--182:6, Jun, 2019. [doi>10.1145/3316781.3317813] - S. M. H. Ho and H. K. H. So, "NnCore: A parameterized non-linear function generator for machine learning applications in FPGAs," in
*2017 International Conference on Field Programmable Technology (ICFPT)*, pp. 160-167, Dec, 2017. [doi>10.1109/FPT.2017.8280134] - S. M. H. Ho, M. Wang, H. C. Ng, and H. K. H. So, "Towards FPGA-assisted Spark: An SVM training acceleration case study," in
*2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)*, pp. 1-6, Nov, 2016. [doi>10.1109/ReConFig.2016.7857194]

## Graph Processing on FPGA

- N. Engelhardt and H. K.-H. So, "GraVF-M: Graph Processing System Generation for Multi-FPGA Platforms,"
*ACM Trans. Reconfigurable Technol. Syst.*, vol. 12, no. 4, pp. 21:1--21:28, November, 2019. [doi>10.1145/3357596][arxiv preprint] - N. Engelhardt and H. K. H. So, "GraVF: A vertex-centric distributed graph processing framework on FPGAs," in
*2016 26th International Conference on Field Programmable Logic and Applications (FPL)*, pp. 1-4, Aug, 2016. [doi>10.1109/FPL.2016.7577360] [pdf] [BibTex] - N. Engerhardt, D. C.-H. Hung, and H. K.-H. So, "Performance-Driven System Generation for Distributed Vertex-Centric Graph Processing on Multi-FPGA Systems," in
*2018 28th International Conference on Field Programmable Logic and Applications (FPL)*, pp. 215-2153, Aug, 2018. [doi>10.1109/FPL.2018.00043] [pdf] - N. Engelhardt and H. K.-H. So, "Towards Flexible Automatic Generation of Graph Processing Gateware," in
*Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies*, pp. 5:1--5:6, Jun, 2017. [doi>10.1145/3120895.3120896] [pdf]

## Imaging Hardware & Applications

- R. Shi, J. S. J. Wong, E. Y. Lam, K. K. Tsia, and H. K.-H. So, "A Real-Time Coprime Line Scan Super-Resolution System for Ultra-Fast Microscopy,"
*IEEE Transactions on Biomedical Circuits and Systems*, vol. 13, no. 4, pp. 781-792, Aug, 2019. [doi>10.1109/TBCAS.2019.2914946] - R. Shi, J. S. J. Wong, and H. K.-H. So, "High-Throughput Line Buffer Microarchitecture for Arbitrary Sized Streaming Image Processing,"
*Journal of Imaging*, vol. 5, no. 3, Mar, 2019. [doi>10.3390/jimaging5030034] - N. Meng, E. Lam, K. K. M. Tsia, and H. K.-H. So, "Large-scale Multi-class Image-based Cell Classification with Deep Learning,"
*IEEE Journal of Biomedical and Health Informatics*, vol. 23, no. 5, pp. 2091-2098, Sep, 2019. [doi>10.1109/JBHI.2018.2878878] - A. C. S. Chan, H.-C. Ng, S. C. V. Bogaraju, H. K. H. So, E. Y. Lam, and K. K. Tsia, "All-passive pixel super-resolution of time-stretch imaging,"
*Scientific Reports*, vol. 7, no. 44608, Mar, 2017. [doi>10.1038/srep44608] - Q. T. K. Lai, K. C. M. Lee, A. H. L. Tang, K. K. Y. Wong, H. K. H. So, and K. K. Tsia, "High-throughput time-stretch imaging flow cytometry for multi-class classification of phytoplankton,"
*Opt. Express*, vol. 24, no. 25, pp. 28170--28184, Dec, 2016. [doi>10.1364/OE.24.028170] - X. Sun, N. H. C. Yung, E. Y. Lam, and H. K. H. So, "Computationally Efficient Hyperspectral Data Learning Based on the Doubly Stochastic Dirichlet Process,"
*IEEE Transactions on Geoscience and Remote Sensing*, vol. 55, no. 1, pp. 363-374, Jan, 2017. [doi>10.1109/TGRS.2016.2606575]

## Advanced Arithmetic Circuits

- M. K. Jaiswal and H. K.-H. So, "PACoGen: A Hardware Posit Arithmetic Core Generator,"
*IEEE Access*, vol. 7, pp. 74586-74601, Jun, 2019. [doi>10.1109/ACCESS.2019.2920936] - M. K. Jaiswal and H. K.-H. So, "Design of quadruple precision multiplier architectures with SIMD single and double precision support,"
*Integration*, vol. 65, pp. 163 - 174, Mar, 2019. [doi>https://doi.org/10.1016/j.vlsi.2018.12.002] - M. K. Jaiswal and H. K.-H. So, "An Unified Architecture for Single, Double, Double-Extended, and Quadruple Precision Division,"
*Circuits, Systems, and Signal Processing*, vol. 37, no. 1, pp. 383--407, Jan, 2018. [doi>10.1007/s00034-017-0559-9] [pdf] - M. K. Jaiswal and H. K.-H. So, "Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division,"
*IEEE Transactions on Circuits and Systems I: Regular Papers*, vol. 64, no. 2, pp. 386-398, Feb, 2017. [doi>10.1109/TCSI.2016.2607227] [pdf] - M. K. Jaiswal, B. S. C. Varma, H. K. H. So, M. Balakrishnan, K. Paul, and R. C. C. Cheung, "Configurable Architectures for Multi-Mode Floating Point Adders,"
*IEEE Transactions on Circuits and Systems I: Regular Papers*, vol. 62, no. 8, pp. 2079-2090, Aug, 2015. [doi>10.1109/TCSI.2015.2452351] [pdf] - M. K. Jaiswal and H. K.-K. So, "Architecture Generator for Type-3 Unum Posit Adder/Subtractor," in
*2018 IEEE International Symposium on Circuits and Systems (ISCAS)*, pp. 1-5, May, 2018. [doi>10.1109/ISCAS.2018.8351142] - M. K. Jaiswal and H. K.-H. So, "Universal number posit arithmetic generator on FPGA," in
*2018 Design, Automation Test in Europe Conference Exhibition (DATE)*, pp. 1159-1162, March, 2018. [doi>10.23919/DATE.2018.8342187]

### Previous Work

- BORPH: Operating System for Reconfigurable Computers